Motivation of the Program

italian version

 

PLL devices were introduced in 1932 and they soon became a very useful circuit in the electronics field, both analog and digital, in a wide range of applications. As an example, among all we can list:

  1. -clock and data recovery;

  2. -phase shifter;

  3. -frequency synthesis;

  4. -frequency synchronization;

  5. -modulation and demodulation (FM or frequency, PM or phase) and digital tuning systems;

  6. -carrier recovery;

- motor control.


Many PLL architectures were proposed in the past, almost always based on a purely analog device or with the possibility of acting on a specific analogic parameter of a digital device (i.e. changing the power supply).

Then, new all-digital architectures were proposed and became available for the PLL design. Such architectures have no dependency on any analogic or passive component, like resistors on capacitors. This components are the main cause of failures, in case of presence of parasitic elements or during the interaction with ionizing radiation.


All-digital PLL devices are the optimal candidates for satisfying the Moore's law, due to their reduced costs and a small occupancy of silicon area; another advantage is the digital design flow, which is much simpler than the analogic design flow.

Moreover, an all-digital PLL has a low sensitivity to the noise sources and to the variations of power supply due to the temperature drift and aging (the so-called PVT parameters: Process, Voltage and Temperature).


The conclusion is that the all-digital design approach can definitely enhance the performances of the circuits, the spectral characteristics of the signals and the reliability of the system.

 

A PLL device is a particular feedback circuit, which allows the synchronization, in frequency and in phase, of an output signal (usually produced by an internal oscillator) with an input reference signal.

When this synchronization is achieved, the phase error between the output signal and the reference is zero or has a constant value.

When the phase difference between the two signals changes, a control system acts on the internal oscillator, in order to minimize the phase difference.

A PLL device can be also used for the production of an output signal with a frequency multiple of the reference frequency: this functionality of the PLL is called frequency synthesis.

 

Objective of the research project is the study and the implementation of all-digital PLL (Phase Locked Loop) and CDR (Clock Data Recovery) devices. The objective will be reached via the development and the prototyping of the all-digital architectures in FPGA and a further implementation in ASIC.

The development and the implementation of all-digital PLL and CDR devices will open, as a consequence, the possibility to design robust devices against Single Event Upset (SEU) and, thus, more reliable and fit for the deployment in radiation environment. Choosing a specific technology process could guarantee a good robustness against total ionizing dose effects (TID). Moreover, all-digital PLL could enhance the knowledge for the design of FPGA-based serial links at Gb/s, which could be cost effective and radiation-tolerant.